Computers have become an integral tool used in a wide variety of different applications, such as in finance and commercial transactions, computer-aided design and manufacturing, health-care, telecommunication, education, etc. Computers are finding new applications as a result of advances in hardware technology and rapid development in software technology. Furthermore, a computer system's functionality is dramatically enhanced by coupling stand-alone computers together to form a computer network. In a computer network, users may readily exchange files, share information stored on a common database, pool resources, and communicate via e-mail and via video teleconferencing.
One popular type of computer network is known as a local area network (LAN). LANs connect multiple computers together such that the users of the computers can access the same information and share data. Typically, in order to be connected to a LAN, a general purpose computer requires an expansion board generally known as a network interface card (NIC). Essentially, the NIC works with the operating system and central processing unit (CPU) of the host computer to control the flow of information over the LAN. Some NICs may also be used to connect a computer to the Internet.
Much of a computer system's functionality and usefulness to a user is derived from the functionality of the peripheral devices. For example, the speed and responsiveness of the graphics adapter is a major factor in a computer system's usefulness as an entertainment device. Or, for example, the speed with which video files can be retrieved from a hard drive and played by the graphics adapter determines the computer system's usefulness as a training aid. Hence, the rate at which data can be transferred among the various peripheral devices often determines whether the computer system is suited for a particular purpose. The electronics industry has, over time, developed several types of bus architectures. Recently, the PCI (peripheral component interconnect) bus architecture has become one of the most widely used, widely supported bus architectures in the industry. The PCI bus was developed to provide a high speed, low latency bus architecture from which a large variety of systems could be developed.
Prior Art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102, main memory 104, cache memory 105 all of which are coupled to a host PCI bridge containing arbiter 106 (hereafter arbiter 106) through a CPU local bus 108 and memory buses 110a and 110b, respectively. A PCI bus 112 is coupled to arbiter 106, and PCI bus 112 is further coupled to each of plurality of PCI agents 114, 116, 118, 120, 122, 124. Note that peripheral component 124 of Prior Art FIG. 1 is a NIC.
Referring still to Prior Art FIG. 1, each of PCI agents 114, 116, 118, 120, 122, 124 (hereafter, PCI agents 114-124) residing on PCI bus 112 use PCI bus 112 to transmit and receive data. PCI bus 112 is comprised of functional signal lines, for example, interface control lines, address/data lines, error signal lines, and the like. Each of PCI agents 114-124 are coupled to the functional signal lines comprising PCI bus 112. When one of PCI agents 114-124 requires the use of PCI bus 112 to transmit data, it requests PCI bus ownership from arbiter 106. The PCI agent requesting ownership is referred to as an "initiator", or bus master. Upon being granted ownership of PCI bus 112 from arbiter 106, the initiator (e.g., PCI agent 116) carries out its respective data transfer.
Each of PCI agents 114-124 may independently request PCI bus ownership. Thus, at any given time, several of PCI agents 114-124 may be requesting PCI bus ownership simultaneously. Where there are simultaneous requests for PCI bus ownership, arbiter 106 arbitrates between requesting PCI agents to determine which requesting PCI agent is granted PCI bus ownership. When one of PCI agents 114-124 is granted PCI bus ownership, it initiates it transaction (e.g., data transfer) with a "target" or slave device (e.g., main memory 104). When the data transaction is complete, the PCI agent relinquishes ownership of the PCI bus, allowing arbiter 106 to reassign PCI bus 112 to another requesting PCI agent.
Thus, only one data transaction can take place on a PCI bus at any given time. In order to maximize the efficiency and data transfer bandwidth of PCI bus 112, PCI agents 114-124 follow a definitive set of protocols and rules. These protocols are designed to standardize the method of accessing, utilizing, and relinquishing PCI bus 112, so as to maximize its data transfer bandwidth. The PCI bus protocols and specifications are set forth in an industry standard PCI specification (e.g., PCI Specification--Revision 2.1). Where each of PCI agents 114-124 are high performance, well designed devices, data transfer rates of up to 528 Mbytes per second can be achieved (e.g., PCI bus 112 operating at 66 MHz).
The NIC, like other peripheral component devices, requires a device driver which controls the physical functions of the NIC and coordinates data transfers between the NIC and the host operating system. An industry standard for interfacing between the device driver and the host operating system is known as the Network Device Interface Specification, or NDIS, which is developed by Microsoft Corporation of Redmond, Washington. The operating system layer implementing the NDIS interface is generally known as an NDIS wrapper. Functionally, the NDIS wrapper arbitrates the control of the device driver between various application programs and provides temporary storage for the data packets.
During typical operation, a peripheral component will need to access data stored in the host computer. In one type of operation, the peripheral component will read data stored in the cache memory of the host computer. In such a read operation, the peripheral component issues a read request to the host computer. In a conventional prior art read operation, the peripheral component will request to read as much of a given type of data as is present in the host computer. In another typical operation, the peripheral component writes information to the memory of the host computer.
Upon receiving the read request, the host computer typically performs a prefetch operation. Specifically, in a conventional prior art prefetch operation the memory subsystem, controlled by the CPU of the host computer, transfers the requested data from system memory of the host computer to cache memory of the host computer. For example, in a conventional prefetch operation, CPU 102 of Prior Art FIG. 1 would transfer data, which a peripheral component (114-124) has requested to read, from system memory 104 to cache memory 105.
In most PCI-based systems, CPU controlled prefetching operations are based on memory line boundaries, such as, cache line boundaries. That is, in conventional operations such as memory read (MR), memory read line (MRL), and memory read multiple (MRM) operations, data is prefetched from a starting address up to a cache line. These conventional prefetch operations have been tailored such that they require minimal CPU overhead and utilization. Additionally, such conventional memory boundary based transfer operations have been designed to provide the most efficient transfer of data between system and cache memory.
Conventional peripheral components, however, simply request to read whatever amount of data is necessary. As a result, in conventional systems, the CPU must account for the fact that the requested data will not occupy an integer number of lines of cache memory. For example, the CPU must write extraneous data into unused portions of a cache line. This, accommodation for data transfers which are not integers of a cache line introduces additional CPU overhead and increases CPU utilization in conventional systems.
Thus, a need exists for a system and method which minimizes the CPU overhead associated with data transfers between a peripheral component and the memory of a host computer system. A further need exists for a system and method which takes advantage of a PCI-based system's inherent use of memory line sizes and boundaries during data transfers.